(1) Field of the Invention
This invention relates to semiconductor integrated circuit devices, and more particularly to a method for fabricating dynamic random access memory (DRAM) devices with an array of memory cells having capacitor-under-bit line (CUB). At the same time the process integration forms tungsten landing plug contacts in the cell areas and peripheral areas of the DRAM chip that reduce the aspect ratio for the multilevel contacts The tungsten landing plug contacts include a unique barrier layer of TiN/Ti/N.sup.+ polysilicon, that prevents dopant depletion from the substrate and forms titanium silicide (TiSi.sub.2) contacts with lower contact resistance (R.sub.c) to the substrate
(2) Description of the Prior Art
Dynamic random access memory (DRAM) circuits are used extensively in the electronics industry for storing data. Each memory cell consists of a single capacitor and a field effect transistor as a charge transfer transistor The binary data (1's and 0's) is stored as electrical charge on the capacitor in the individual memory cells. The number and density of these memory cells on the DRAM chip has dramatically increased in recent years and by the year 2000 the number of memory cells on a chip is expected to reach 1 Gigabit. This increase in circuit density has resulted from the downsizing of the individual semiconductor devices (FETs) and the resulting increase in device packing density The reduction in device size is due in part to advances in high-resolution photolithography and directional (anisotropic) plasma etching. However, as the horizontal device feature sizes are scaled down to submicrometer dimensions, it is necessary to use self-alignment techniques to relax the alignment requirements and improve critical dimension (CD) control.
Unfortunately, as the horizontal dimensions continue to decrease, while the vertical dimensions remain essentially constant, the aspect ratio (depth to width) increases and it becomes increasing difficult to etch reliable contact holes This is a particular problem when etching the multilevel contact openings on the DRAM devices. One method for reducing the difficulties of etching high aspect ratio contact holes on DRAMs is described in U.S. Pat. No. 5,332,685 to Park et al. In this approach a polysilicon or metal is formed by selective deposition or by deposition and etching back to form contact plugs in the contact holes in the insulating layer on the substrate. Park et al. then form the stacked capacitors and bit lines on the contact plugs adjacent to each other. However, since the capacitors and bit lines lie in the same plane, the size of the capacitor and packing density are limited. Another method for making DRAM memory cells is the Capacitor-Under-Bit line (CUB) structure described in U.S. Pat. No. 5,648,291 to Sung in which the bit line contact is made self-aligned to the adjacent stacked capacitor. However, the method requires a high-aspect-ratio contact hole for the bit line, which is increasingly difficult to make as the minimum feature sizes decrease. Still another method for making DRAMs is described in U.S. Pat. No. 5,045,899 to Arimoto. The bit line contact and bit line are formed between and adjacent to the stacked capacitors so as to suppress the stray bit line capacitance for improved circuit performance The problem of making multilevel contact holes with high aspect ratios is not addressed. Therefore, there is still a need to improve the DRAM process so as to minimize the aspect ratios of the multilevel contacts holes on the DRAM chip during downscaling of the minimum feature sizes of the devices.
Another problem associated with increased packing density is the increased contact resistance (R.sub.c) with reduced minimum feature size of the contact hole and the formation of shallower diffused junction depths in the FET source/drain contact areas to improve the FET electrical characteristics. One approach is to replace the more conventional doped polysilicon plugs with tungsten (W) metal plugs using a titanium/titanium nitride (Ti/TiN) barrier/adhesion layer.
This approach is described by Somekh et al. in U.S. Pat. No. 5,250,467, in which a Ti barrier layer is deposited in the contact holes using a conventional PVD sputtering process and annealed in nitrogen to form a TiSi.sub.2 with the doped silicon substrate contact and concurrently a top TiN layer. The W plug is then formed by CVD deposition using tungsten hexafluoride. However, Somekh et al. do not address the problem of depletion of the dopant from the substrate contact during TiSi.sub.2 formation that would also increase the contact resistance (R.sub.c). Another method of making W/TiN contacts is described by Pinchovski et al., U.S. Pat. No. 4,822,753, in which a self-aligned titanium silicide (salicide) is used, and then a TiN layer is deposited as a barrier/adhesion layer. However, the depletion of dopant from the shallow diffused junction in the substrate contact during the TiSi.sub.2 formation is not addressed.
Therefore there is still a need in the semiconductor industry to provide a very manufacturable cost-effective process that increases the memory cell density on the DRAM chip while reducing the aspect ratio of the multilevel contact and reducing contact resistance (R.sub.c).